View UCC28051_6407437.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

slus515b?september 2002 ? revised june 2003 1 www.ti.com features transition mode pfc controller for low implementation cost industry pin compatibility with improved feature set improved transient response with slew-rate comparator zero power detect to prevent ovp during light load conditions accurate internal v ref for tight output regulation two uvlo options overvoltage protection (ovp), open-feedback protection and enable circuits 750-ma peak gate drive current low start-up and operating currents applications switch-mode power supplies for desktops, monitors, tvs and set top boxes (stbs) ac adapter front-end power supplies electronic ballasts description the ucc38050 and ucc38051 are pfc controllers for low-to-medium power applications requiring compliance with iec 1000-3-2 harmonic reduction standard. it is designed for controlling a boost preregulator operating in transition mode (also referred to as boundary conduction mode or critical conduction mode operation). it features a transconductance voltage amplifier for feedback error processing, a simple multiplier for generating a current command proportional to the input voltage, a current-sense (pwm) comparator, pwm logic and a totem-pole driver for driving an external fet. simplified application diagram udg?02125 1 2 3 4 8 7 6 5 vcc drv gnd zcd vo_sns comp multin cs ucc38050 copyright ? 2002, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
slus515b ? september 2002 ? revised june 2003 2 www.ti.com description (continued) in the transition mode oepration, the pwm circuit is self-oscillating with the turn-on being governed by an inductor zero-current detector (zcd pin) and the turn-off being governed by the current-sense comparator. additionally, the controller provides features such as peak current limit, default timer, overvoltage protection (ovp) and enable. the ucc38050 and ucc38051, while being pin compatible with other industry controllers providing similar functionality, offer many feature enhancements and tighter specifications, leading to an overall reduction in system implementation cost. the system performance is enhanced by incorporation of zero power detect function which allows the controller output to shut down at light load conditions without running into overvoltage. the device also features innovative slew rate enhancement circuits which improve the large signal transient performance of the voltage error amplifier. the low start-up and operating currents of the device results in low power consumption and ease of start-up. highly accurate internal bandgap reference leads to tight regulation of output voltage in normal and ovp conditions, resulting in higher system reliability. the enable comparator ensures that the controller is off if the feedback sense path is broken or if the input voltage is very low. there are two key parameteric differences between ucc38050 and ucc38051. the uvlo turn-on threshold of ucc38050 is 15.8 v while for ucc38051 it is 12.5 v. secondly, the g m amplifier ? s source current for ucc38050 is typically 1.3 ma while for ucc38051 it is 180 a. the higher uvlo turn-on threshold of the ucc38050 allows quicker and easier start-up with a smaller v cc capacitance while the lower uvlo turn-on threshold of ucc38051 allows the operation of the pfc chip to be easily controlled by the downsteam pwm controller in two-stage power converters. the ucc38050 g m amplifier also provides a full 1.3-ma typical source current for faster start-up and improved transient response when output is low either at start-up or during transient conditions. the ucc38051 scales this source current back down to 180- a typical source current to gradually incr ease the error voltage preventing a step increase in line currents at start-up but still provides good transient response. the ucc38051 is suitable for multiple applications including ac adapters where a two-stage power conversion is needed. the ucc38050 is suitable for applications such as electronic ballasts where there is no down-stream pwm conversion and the advantages of smaller v cc capacitor and improved transient response can be realized. devices are available in either the industrial temperature range of ? 40 c to 105 c (ucc2805x) or commercial temperature range of 0 c to 70 c (ucc3805x). package offerings are 8-pin soic (d) or 8-pin pdip (p) packages. ordering information tt uvlo threshold voltage on/off g m amplifier so rce c rrent packaged devices (1) t a = t j voltage on/off (v) source current ( a) soic-8 (d) pdip-8 (p) 40 c to 105 c 15.8 / 9.7 ? 1300 ucc28050d ucc28050p ? 40 c to 105 c 12.5 / 9.7 ? 180 UCC28051d UCC28051p 0 cto70 c 15.8 / 9.7 ? 1300 ucc38050d ucc38050p 0 c to 70 c 12.5 / 9.7 ? 180 ucc38051d ucc38051p (1) d (soic-8) package is available taped and reeled. add r suffix to device type (e.g. ucc28050dr) to order quantities of 2,500 devices per reel.
slus515b ? september 2002 ? revised june 2003 3 www.ti.com connection diagram (top view) gnd drv vcc zcd comp vo_sns multin cs 1 2 3 4 8 7 6 5 d or p package absolute maximum ratings over operating free-air temperature range unless otherwise noted (1) uccx805x unit supply voltage, v cc (internally clamped) 20 v input current into v cc clamp i dd 30 input current zcd 10 ma gate drive current (peak), i drv drv 750 ma input voltage range, v cc vo_sns, multin, cs 5 v maximum negative voltage vo_sns, multin, drv, cs ? 0.5 v power dissipation at t 25 c d package 650 mw power dissipation at t a = 25 c p package 1 w operating junction temperature range, t j ? 55 to 150 storage temperature, t stg ? 65 to 150 c lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 c (1) stresses beyond those listed under ? absolute maximum ratings ? may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under ? recommended operating conditions ? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. all voltages are with respect to gnd. currents are positive into, negative out of the specified terminal.
slus515b ? september 2002 ? revised june 2003 4 www.ti.com electrical characteristics t a = 0 c to 70 c for the ucc3805x, ? 40 c to 105 c for the ucc2805x, t a = t j , v cc = 12 v. supply parameter test conditions min typ max units v cc operating voltage 18 v shunt voltage i vcc = 25 ma 18 19 20 v supply current, off v cc = v cc turn ? on threshold ? 300 mv 75 125 a supply current, disabled vo_sns = 0.5 v 2 4 supply current, on 75 khz, c l = 0 nf 4 6 ma supply current, dynamic operating 75 khz, c l = 1 nf 5 7 ma uvlo parameter test conditions min typ max units v t rn on threshold uccx8050 15.4 15.8 16.4 v cc turn-on threshold uccx8051 12.0 12.5 13.0 v cc turn-off threshold 9.4 9.7 10.0 v uvlo h steresis uccx8050 5.8 6.3 6.8 v uvlo hysteresis uccx8051 2.3 2.8 3.3 voltage amplifier (vo_sns) parameter test conditions min typ max units input voltage (v ) ucc3805x 2.46 2.50 2.54 v input voltage (v ref ) ucc2805x 2.45 2.50 2.55 v input bias current 0.5 a v comp high vo_sns = 2.1 v 4.5 5.5 v v comp low vo_sns = 2.55 v 1.80 2.45 v g m t j = 25 c, v comp = 3.5 v 60 90 130 s source current uccx8050 vo sns 2 1 v v 3 5 v ? 0.2 ? 1.0 ma source current uccx8051 vo_sns = 2.1 v, v comp = 3.5 v ? 120 ? 180 ? 240 a sink current vo_sns = 2.7 v v comp = 3.5 v 0.2 1.0 ma over voltage protection / enable parameter test conditions min typ max units overvoltage reference uccx8050 vref + 0.165 vref + 0.190 vref + 0.210 v overvoltage reference uccx8051 vref + 0.150 vref + 0.180 vref + 0.210 v hysteresis uccx8050 175 200 225 mv hysteresis uccx8051 150 180 210 mv enable threshold 0.62 0.67 0.72 v enable hysteresis 0.05 0.10 0.20 v multiplier parameter test conditions min typ max units multiplier gain constant (k) v multin = 0.5 v, comp = 3.5 v 0.43 0.65 0.87 1/v dynamic input range, v multin input 0 to 2.5 0 to 3.5 v dynamic input range, comp input 2.5 to 3.8 2.5 to 4.0 v input bias current, multin 0.1 1.0 a
slus515b ? september 2002 ? revised june 2003 5 www.ti.com electrical characteristics t a = 0 c to 70 c for the ucc3805x, ? 40 c to 105 c for the ucc2805x, t a = t j , v cc = 12 v. zero power parameter test conditions min typ max units zero power comparator threshold (1) measured on v comp 2.1 2.3 2.5 v zero current detect parameter test conditions min typ max units input threshold (rising edge) (1) 1.5 1.7 2.0 v hysteresis (1) 250 350 450 mv input high clamp i = 3 ma 5 6 v input low clamp i = ? 3 ma 0.30 0.65 0.90 v restart time delay 200 400 s current sense comparator parameter test conditions min typ max units input bias current cs = 0 v 0.1 1.0 a input offset voltage (1) ? 10 10 mv delay to output cs to drv 300 450 ns maximum current sense threshold voltage 1.55 1.70 1.80 v pfc gate driver parameter test conditions min typ max units gt1 pull up resistance i out = ? 125 ma 5 12 ? gt1 pull down resistance i out = 125 ma 2 10 ? gt1 output rise time c load = 1 nf, r load = 10 ? 25 75 ns gt1 output fall time c load = 1 nf, r load = 10 ? 10 50 ns (1) ensured by design. not production tested.
slus515b ? september 2002 ? revised june 2003 6 www.ti.com block diagram udg ? 02008 1 2 5 6 7 8 3 4 5 pf + + + x x mult 2.5 v 2.3 v + + ovp enable 2.7/2.5 v gm vol. error amp 0.67/0.57 v pwm sq q r + timer + int. bias 1.7/1.4 v uvlo ovp vo_sns comp multin cs zcd gnd drv vcc ref zero power detect v ref & bias reg v ref v ref good 40 k ? pin descriptions vo_sns (pin 1): this pin senses the boost regulator output voltage through a voltage divider. internally, this pin is the inverting input to the transconductance amplifier (with a nominal value of 2.5 v) and also is input to the ovp comparator. additionally, pulling this pin below 0.50 v turns off the output switching, ensuring that the gate drive is held off while the boost output is pre-charging and also ensuring no runaway if feedback path is open. comp (pin 2): output of the transconductance error amplifier. loop compensation components are connected between this pin and ground. the output current capability of this pin is 10- a under normal conditions, but increases to about 1-ma when the differential input is greater than the specified values in the specifications table. this voltage is one of the inputs to the multiplier, with a dynamic input range of 2.5 v to 3.8 v. during zero power or overvoltage conditions, this pin goes below 2.5 v nominal. when it goes below 2.3 v, the zero power comparator is activated which prevents the gate drive from switching. multin (pin 3): this pin senses the instantaneous boost regulator input voltage through a voltage divider. the voltage acts as one of the inputs to the internal multiplier. recommended operating range is 0 v to 2.5 v at high line.
slus515b ? september 2002 ? revised june 2003 7 www.ti.com pin descriptions (continued) cs (pin 4): this pin senses the instantaneous switch current in the boost switch and uses it as the internal ramp for pwm comparator. the internal circuitry filters out switching noise spikes without requiring external components. in addition, an external r-c filter may be required to suppress the noise spikes. an internal clamp on the multiplier output terminates the switching cycle if this pin voltage exceeds 1.7 v. additional external filtering may be required. cs threshold is approximately equal to: v cs 0.67 ( comp 2.5 v ) multin v offset v offset is approximately 75 mv to improve the zero crossing distortion. zcd (pin 5): this pin is the input for the zero current detect comparator. the boost inductor current is indirectly sensed through the bias winding on the boost inductor. the zcd pin input goes low when the inductor current reaches zero and that transition is detected. internal active voltage clamps are provided to prevent this pin from going below ground or too high. if zero current is not detected within 400 s, a reset timer sets the latch and gate drive. gnd (pin 6): the chip reference ground. all bypassing elements are connected to ground pin with shortest loops feasible. drv (pin 7): the gate drive output for an external boost switch. this output is capable of delivering up to 750-ma peak currents during turn-on and turn-off. an external gate drive resistor may be needed to limit the peak current depending on the v cc voltage being used. below the uvlo threshold, the output is held low. vcc (pin 8): the supply voltage for the chip. this pin should be bypassed with a high-frequency capacitor (greater than 0.1- f) and tied to gnd. the ucc38050 has a wide uvlo hysteresis of approximately 6.3 v that allows use of lower value supply capacitor on this pin for quicker and easier start-up. the ucc38051 has a narrow uvlo hysteresis with of about 2.8 v and a start-up voltage of about 12.5 v for applications where the operation of the pfc device needs to be controlled by a downstream pwm controller.
slus515b ? september 2002 ? revised june 2003 8 www.ti.com block description uvlo and reference block this block generates a precision reference voltage used to obtain tightly controlled uvlo threshold. in addition to generating a 2.5-v reference for the non-inverting terminal of the g m amplifier, it generates the reference voltages for blocks such as ovp, enable, zero power and multiplier. an internal rail of 7.5 v is also generated to drive all the internal blocks. error amplifier the voltage error amplifier in ucc3805x is a transcoductance amplifier with a typical transconductance value of 90 s. the advantage in using a transconductance amplifier is that the inverting input of the amplifier is solely determined by the external resistive-divider from the output voltage and not the transient behavior of the amplifier itself. this allows the vo_sns pin to be used for sensing over voltage conditions. the sink and source capability of the error amplifier is approximately 10 a during normal operation of the amplifier. but when the vo_sns pin voltage is beyond the normal operating conditions (vo_sns >1.05 v ref , vo_sns < 0.88 v ref ), additional circuitry to enhance the slew-rate of the amplifier is activated. enhanced slew-rate of the compensation capacitor results in a faster start-up and transient response. this prevents the output voltage from drifting too high or too low, which can happen if the compensation capacitor were to be slewed by the normal slewing current of 10- a. when vo_sns rises above the normal range, the enhanced sink current capability is in excess of 1 ma. when vo_sns falls below the normal range, the ucc38050 can source more than 1 ma and the ucc38051 sources approximately 180 a. the limited source current in the ucc38051 helps to gradually increase the error voltage on the comp pin preventing a step increase in line current. the actual rate of increase of v comp depends on the compensation network connected to the comp pin. zero current detection and re-start timer blocks when the boost inductor current becomes zero, the voltage at the power mosfet drain end falls. this is indirectly sensed with a secondary winding that is connected to the zcd pin. the internal active clamp circuitry prevents the voltage from going to a negative or a high positive value. the clamp has the sink and source capability of 10 ma. the resistor value in series with the secondary winding should be chosen to limit the zcd current to less than 10 ma. the rising edge threshold of the zcd comparator can be as high as 2.0 v. the auxiliary winding should be chosen such that the positive voltage (when the power mosfet is off) at the zcd pin is in excess of 2.0 v. the restart timer attempts to set the gate drive high in case the gate drive remains off for more than 400 s nominally. the minimum guaranteed time period of the timer is 200 s. this translates to a minimum switching frequency of 5 khz. in other words, the boost inductor value should be chosen for switching frequencies greater than 5 khz. enable block the gate drive signal is held low if the voltage at the vo_sns pin is less than 0.67 v which translates to a output voltage of about 115 v. this feature can be used to disable the converter by pulling vo_sns below 0.5 v (overcoming hysteresis). if the output feedback path is broken, vo_sns is pulled to ground and the output is disabled to protect the power stage.
slus515b ? september 2002 ? revised june 2003 9 www.ti.com block description (continued) zero power block when the output of the g m amplifier goes below 2.3 v, the zero power comparator latches the gate drive signal low. the slew rate enhancement circuitry of the g m amplifier that is activated during overvoltage conditions slews the comp pin to about 2.4 v. this ensures that the zero power comparator is not activated during transient behavior (when the slew rate enhancement circuitry is enhanced). multiplier block the multiplier block has two inputs. one is the error amplifier output voltage (v comp ), while the other is v multin which is obtained by a resistive divider from the rectified line. the multiplier output is approximately 0.67 v multin (v comp ? 2.5 v). there is a positive offset of about 75 mv to the v multin signal because this improves the zero-crossing distortion and hence the thd performance of the controller in the application. the dynamic range of the inputs can be found in the electrical characteristics table. overvoltage protection (ovp) block the ovp feature in the part is not activated under most operating conditions because of the presence of the slew rate enhancement circuitry present in the error amplifier. as soon as the output voltage reaches to about 5% above the nominal value, the slew rate enhancement circuit is activated and the error amplifier output voltage is pulled below the dynamic range of the multiplier block. this prevents further rise in output voltage. if the comp pin is not pulled low fast enough, and the voltage rises further, the ovp circuit acts as a second line of protection. when the voltage at the vo_sns pin is more than 7.5% of the nominal value ( >(v ref +0.190)), the ovp feature is activated. it stops the gate drive from switching as long as the voltage at the vo_sns pin is above the nominal value (v ref ). this prevents the output dc voltage from going above 7.5% of the nominal value designed for, and protects the switch and other components of the system like the boost capacitor. transition mode control the boost converter, the most common topology used for power factor correction, can operate in two modes ? continuous conduction code (ccm) and discontinuous conduction mode (dcm). transition mode control, also referred to as critical conduction mode (crm) or boundary conduction mode, maintains the converter at the boundary between ccm and dcm by adjusting the switching frequency. the crm converter typically uses a variation of hysteretic control with the lower boundary equal to zero current. it is a variable frequency control technique that has inherently stable input current control while eliminating reverse recovery rectifier losses. as shown in figure 1, the switch current is compared to the reference signal (output of the multiplier) directly. this control method has the advantage of simple implementation and still can provide very good power factor correction.
slus515b ? september 2002 ? revised june 2003 10 www.ti.com typical application diagram udg ? 02008 1 2 5 6 7 8 3 4 40 k ? 5 pf + + + x x mult 2.5 v 2.3 v + + ovp enable 2.7/2.5 v error amp 0.67/0.57 v pwm sq q r + timer + v ref int. bias 1.7 v/1.4 v uvlo v ref good ovp vo_sns comp multin cs zcd gnd drv vcc + ? l r g1 r s1 c out r up r ac1 r o2 r v1 c v1 r ac2 c v2 r v1 zero power detect g m vol. r o1 v ref and bias reg c b r b c ac1 c s1 r zc ref
slus515b ? september 2002 ? revised june 2003 11 www.ti.com application information udg ? 02124 + c d load + r iac x x mult l sq r q gate driver logic v ac i ac z cd i mo v ea v ref figure 1. basic block diagram of crm boost pfc the power stage equations and the transfer functions of the crm are the same as the ccm. however, implementations of the control functions are different. transition mode forces the inductor current to operate just at the border of ccm and dcm. the current profile is also different and affects the component power loss and filtering requirements. the peak current in the crm boost is twice the amplitude of ccm leading to higher conduction losses. the peak-to-peak ripple is twice the average current which affects mosfet switching losses and magnetics ac losses. udg ? 02123 i average (c) crm (b) dcm (a) ccm i peak i average i peak i average note: operating frequency >> 120 hz figure 2. pfc inductor current profiles
slus515b ? september 2002 ? revised june 2003 12 www.ti.com application information for low to medium power applications up to approximately 300 w, the crm boost has an advantage in losses. the filtering requirement is not severe and therefore is not a disadvantage. for medium to higher power applications, where the input filter requirements dominate the size of the magnetics, the ccm boost is a better choice due to lower peak currents (which reduces conduction losses) and lower ripple current (which reduces filter requirements). the main tradeoff in using crm boost is lower losses due to no reverse recovery in the boost diode vs. higher ripple and peak currents. design procedure for a selected v out and minimum switching frequency, the following equations outline the design guidelines for power stage component selection. refer to the typical application diagram for reference designators. inductor selection in the transition mode control, the inductor value needs to be calculated to start the next switching cycle at zero current. the time it takes to reach zero depends on line voltage and inductance and as shown in equation (1), l determines the converter ? s frequency range. l v ac(min) 2 v out 2 v ac(min) 2 f s(min) v out p in where v ac = rms line voltage v ac(min) = minimum ac line voltage p in = maximum input power averaged over the ac line period i l(peak) 2 2 p in v ac(min) i l(rms) i l(peak) 6 mosfet selection the main switch selection is driven by the amount of power dissipation allowable. it is important to choose a device that minimizes gate charge and capacitance and minimizes the sum of switching and conduction losses at a given frequency. i q(rms_crm) 1 6 4 2 v ac(min) 9 v out il peak(crm) v q(max) v out (1) (2) (3) (4) (5)
slus515b ? september 2002 ? revised june 2003 13 www.ti.com application information diode selection the effects of the reverse recovery current in the diode can be eliminated with relatively little negative impact to the system. the diode selection is based on reverse voltage, forward current, and switching speed. i d(avg) i out(avg) i d(rms) i l(peak) 2 v ac v out v d(peak) v out capacitor selection the hold-up time is the main requirement in determining the output capacitance. esr and the maximum rms ripple current rating may also be important especially at higher power levels. c out(min) 2 p out t holdup v out 2 v out(min) 2 where: v out(min) = minimum regulator input voltage for operation i c(rms) i l(peak) 2 2 v ac(max) v out p out v out 2 ( ac rms load currents ) 2 multiplier set-up select r ac1 and r ac2 so that their ratio uses the full dynamic range of the multiplier input at the peak line voltage yet, their values are small enough to make the effects of the multiplier bias current negligible. in order to use the maximum range of the multiplier, select the divider ratio so that v multin evaluated at the peak of the maximum ac line voltage is the maximum of the minimum dynamic input range of multin, which is 2.5 v. choose r ac1 so that it has at least 100- a at the peak of the minimum ac operating line voltage. r ac1 r ac2 2 2.5 v ac(max) 1 in extreme cases, switching transients can contaminate the multin signal and it can be beneficial to add capacitor c ac1 . select the value of c ac1 so that the corner frequency of the resulting filter is greater than the lowest switching frequency. keep in mind that the low corner frequency of this filter may compromise the overall power factor. (6) (7) (8) (9) (10) (11)
slus515b ? september 2002 ? revised june 2003 14 www.ti.com application information sense resistor selection the current sense resistor value must be chosen to limit the output power and it must also use the full dynamic range of the multiplier during normal steady state operation. the value of r s1 is thus selected for maximum power operation at low ac line voltage conditions. in order to use the full dynamic range, set the v sense threshold as a function of the dynamic input range of v comp and the peak of the minimum multin voltage. r s1 0.67 comp (max) comp (min) multin (peak)@vac(min) 0.075 2 2 p in(max) v ac(min) where: comp (max) = 3.8 v comp (min) = 2.5 v multin (peak)@vac(min) 2 v ac(min) r ac2 r ac2 r ac1 if the exact value r s1 is not available. r s2 and r s3 can be added for further scaling. the cs pin already has an internal filter for noise due to switching transients. additional filtering at switching transient frequencies can be achieved by adding c s1 . output voltage sense design select the divider ratio of r o1 and r o2 to set the vo_sns voltage to 2.5 v at the desired output voltage. the current through the divider should be at least 200 a. voltage loop design how well the voltage control loop is designed directly impacts line current distortion. ucc38050 employs a transconductance amplifier (g m amp) with gain scheduling for improved transient response (refer to figure 14. g m amplifier output current vs. current sense voltage ). integral type control at low frequencies is preferred here because the loop gain varies considerably with line conditions. the largest gain occurs at maximum line voltage. if the power factor corrector load is dc-to-dc switching converter, the small signal model of the controller and the power factor corrector, from comp to pfc output voltage is given by: v ^ out (s) v ^ comp (s) k 1 v ac 2 v out(avg) r s1 k crm c out 1 s where: v ^ out = small signal variations in v out v ^ comp = small signal variations in v comp k 1 = multiplier gain = 0.65 k crm = peak to average factor = 2 (12) (13)
slus515b ? september 2002 ? revised june 2003 15 www.ti.com application information a controller that has integral control at low frequencies requires a zero near the crossover frequency in order to be stable. the resulting g m amplifer configuration is shown in figure 3. udg ? 02122 v ref v out + r v1 c v1 c v2 figure 3. g m amplifier configuration the compensator transfer function is: a v g m c v1 c v2 1 r v1 c v1 s s 1 r v1 c v1 c v2
c v1 c v2
s where g m = dc transconductance gain = 100 s the limiting factor of the gain is usually the allowable third harmonic distortion, though other harmonics can dominate. the crossover frequency of the control loop will be much lower than twice the ac line voltage. in order to choose the compensator dynamics, determine the maximum allowable loop gain at twice the line frequency and solve for capacitor c v2 . this also determines the crossover frequency. c v2 v ac(max) 4 f ac 2 g m k 1 v out(avg) r s1 k (crm) c out(max loop gain @ 2 f ac ) f co v ac g m k 1 c v2 v out r s1 k(cmr) c out select c v1 so that the low frequency zero is one-tenth of the crossover frequency. c v1 9c v2 select r v1 so that the pole is at the crossover frequency. r v1 1 2 f co 1 c v1 1 c v2 (14) (15) (16) (17) (18)
slus515b ? september 2002 ? revised june 2003 16 www.ti.com bias current the bias voltage is supplied by a bias winding on the inductor. select the turns ratio so that sufficient bias voltage can be achieved at low ac line voltage. the bias capacitor must be large enough to maintain sufficient voltage with ac line variations. be sure to connect a 0.1- f bypass capacitor between the vcc pin and the gnd pin as close to the integrated circuit as possible. for wide line variations, a resistor, r b , is necessary in order to permit clamping action. the bias voltage should also be clamped with an external zener diode to a maximum of 18 v. zero current detection the zero current detection activates when the zcd voltage falls below 1.4 v. the bias winding can provide the necessary voltage. this pin has a clamp at approximately 5 v. add a current limiting resistor, r zc , to keep the maximum current below 1 ma.
slus515b ? september 2002 ? revised june 2003 17 www.ti.com reference design a reference design is discussed in 100-w universal line input pfc boost converter using the ucc38050, ti literature no. sluu134. the ucc38050 is used for the off-line power factor corrected pre-regulator with operation over a universal input range of 85 v to 265 v with a 400 vdc regulated output. the schematic is shown in figure 4 and the board layout for the reference design is shown in figure 5. refer to the document for further details. + + + figure 4. universal line input 100-w boost converter reference design schematic figure 5. reference design board layout
slus515b ? september 2002 ? revised june 2003 18 www.ti.com typical characteristics figure 6 supply current vs supply voltage i cc ? supply current ? ma v cc ? supply voltage ? v 2.5 3.0 3.5 2.0 4.0 0 0.5 1.0 1.5 20 012 8 416 ucc38051 ucc38050 supply current vs temperature t j ? temperature ? c figure 7 4 5 3 0 1 2 125 ?50 50 25 0 100 ?25 75 i cc ? supply current ? ma i cc = on 75 khz, 1 nf i cc = on 75 khz, no load i cc = on no switching 6 14 16 10 4 6 2 8 12 18 0 125 ?50 50 25 0 100 ?25 75 20 figure 8 uvlo thresholds vs temperature v uvlo ? uvlo threshold voltage ? v t j ? temperature ? c uvlo on (uccx8050) uvlo off uvlo hysteresis (uccx8050) uvlo on (uccx8051) uvlo hysteresis (uccx8051) reference voltage vs temperature v ref ? reference voltage ? v t j ? temperature ? c figure 9 2.54 2.56 2.50 2.60 2.44 2.46 2.42 2.48 2.52 2.58 2.40 12 5 ?50 50 25 0 100 ?25 75
slus515b ? september 2002 ? revised june 2003 19 www.ti.com typical characteristics figure 10 current sense input threshold vs multiplier input voltage v cs ? cs input voltage ? v v multin ? multiplier input voltage ? v 1.2 1.4 0.8 1.8 0.4 0.2 0.6 1.0 1.6 0.0 3.0 0 1.5 1.0 0.5 2.5 2.0 comp = 3.5 v comp = 3.25 v comp = 2.75 v comp = 3 v comp = 3.75 v comp = 2.5 v maximum current sense threshold vs temperature v cs(max) ? maximum current sense threshold ? v t j ? temperature ? c figure 11 12 5 ? 50 50 25 0 100 ? 25 75 1.725 1.750 1.675 1.550 1.600 1.625 1.575 1.650 1.700 1.775 1.800 figure 12 cs to output delay time vs temperature t delay ? cureent sense to output delay time ? ns t j ? temperature ? c 125 ? 50 50 25 0 100 ? 25 75 350 400 250 0 100 150 50 200 300 450 transconductance vs temperature g m ? transconductance ? s t j ? temperature ? c figure 13 125 ? 50 50 25 0 100 ? 25 75 100 90 120 60 70 80 110
slus515b ? september 2002 ? revised june 2003 20 www.ti.com typical characteristics figure 14 g m amplifier output current vs output sense voltage i comp ? gm amplifier output current ? ma v vo_sns ? output sense voltage ? v 2.8 2.0 2.5 2.4 2.2 2.7 2.1 2.6 0.5 0 ? 1.5 ? 1.0 ? 0.5 1.0 2.3 1.5 uccx8051 uccx8050 g m amplifier output current vs output sense voltage (small signal view) i comp ? gm amplifier output current ? ma v vo_sns ? output sense voltage ? v figure 15 2.60 2.40 2.50 2.45 2.55 ? 0.012 ? 0.004 0 0.004 0.008 0.012 ? 0.008 figure 16 voltage amplifier output vs time v comp ? voltage amplifier output ? v 25 s / div 4.5 5.0 3.5 1.5 2.5 2.0 3.0 4.0 5.5 v sense v ao c load = 10 nf overvoltage protection thresholds vs temperature v ovp ? ovp threshold voltage ? v t j ? temperature ? c figure 17 12 5 ? 50 50 25 0 100 ? 25 75 2.65 2.60 2.80 2.40 2.45 2.55 2.75 2.70 2.50 ovp off ovp on
slus515b ? september 2002 ? revised june 2003 21 www.ti.com typical characteristics figure 18 zero current detection clamp current vs voltage i zcd ? zcd current ? ma v zcd ? zcd voltage ? v 7 04 3 26 15 2 0 10 ? 10 ? 8 ? 2 8 6 ? 6 ? 4 4 restart time vs temperature t restart ? restart time ? s t j ? temperature ? c figure 19 125 ? 50 50 25 0 100 ? 25 75 400 300 600 0 100 200 500 figure 20 output saturation voltage vs source current v out(sat) ? output saturation voltage ? v i source ? source current ? ma 700 0 400 300 200 600 100 500 5 4 8 0 1 3 7 800 2 6 vcc = 12 v output saturation voltage vs sink current v out(sat) ? output saturation voltage ? v i sink ? sink current ? ma figure 21 2.5 1.5 0 0.5 1.0 2.0 700 0 400 300 200 600 100 500 800 vcc = 12 v
slus515b ? september 2002 ? revised june 2003 22 www.ti.com mechanical data d (r-pdso-g**) plastic small-outline package 8 pins shown 8 0.197 (5,00) a max a min (4,80) 0.189 0.337 (8,55) (8,75) 0.344 14 0.386 (9,80) (10,00) 0.394 16 dim pins ** 4040047/e 09/01 0.069 (1,75) max seating plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) nom 0 ? 8 gage plane a 0.004 (0,10) 0.010 (0,25) 0.050 (1,27) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). d. falls within jedec ms-012
slus515b ? september 2002 ? revised june 2003 23 www.ti.com mechanical data p (pdip) plastic dual-in-line 8 4 0.015 (0,38) gage plane 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) nom max 0.430 (10,92) 4040082/d 05/98 0.200 (5,08) max 0.125 (3,18) min 5 0.355 (9,02) 0.020 (0,51) min 0.070 (1,78) max 0.240 (6,10) 0.260 (6,60) 0.400 (10,60) 1 0.015 (0,38) 0.021 (0,53) seating plane m 0.010 (0,25) 0.100 (2,54) notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. falls within jedec ms-001 for the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2003, texas instruments incorporated

▲Up To Search▲

Price & Availability of UCC28051

	To Download UCC28051 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .